1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Field Effect Transistors (FETs) have a characteristic in that strain in channel regions improves carrier mobility. “Strain generating techniques” for causing strain in channel regions are attracting increased interest for application to super speed FETs having a gate length of 100 nm or less. FIG. 1A illustrates an example of strain generating methods. According to this method, a silicon (Si) layer having an N-channel region is formed on the surface of a silicon-germanium (SiGe) layer. Thus, a biaxial tensile stress is applied to the N-channel to cause strain therein. FIG. 1B illustrates another example of strain generating methods. According to this method, SiGe layers are embedded into a silicon (Si) layer. Thus, a uniaxial compressive stress is applied to a P-channel region to cause strain therein (see Reference 1: A. Shimizu et al., Tech. Dig. of 2001 IEDM, IEEE, 2001, pp. 443-436; and Reference 2: K. Goto et al., Tech. Dig. of 2004 IEDM, IEEE, 2004, pp. 209-212). In these strain generating methods, the difference between the Si lattice constant and the SiGe lattice constant is a factor in generating a stress.
When a crystal shown in FIG. 2A is strained as illustrated in FIG. 2B, dislocation (FIG. 2C) is activated and expanded in the crystal under high temperature and high stress conditions. The term “dislocation” indicates line crystal defects. The types of dislocation include edge dislocation and screw dislocation. When the dislocation is activated and expanded in the strained crystal, the strain in the crystal is relieved by the dislocation.
The dislocation is not caused by self-nucleation. There is always a source that causes initial dislocation. In the case of the strain generating method of FIG. 1A, the dislocation source may be, for example, through penetration that has occurred when the SiGe layer or the Si layer is formed. In the case of the strain generating method of FIG. 1B, the dislocation source may be, for example, a lattice defect due to etching damage caused when grooves for layer embedment are formed. The (111) facet produced during the etching process also causes lattice defects. When the wafer is processed at high temperature, the initial dislocation is activated in the Si layer or the SiGe layers and expanded in the Si layer or the SiGe layers, as illustrated in FIG. 3. The quantity of strain ΔX after dislocation is produced is expressed asΔX=ΔX0−A|b|N where X0 is an initial strain, N is a density of dislocation in the system, A is a constant of proportion, and b is a Burger's vector (|b| denotes the size of the Burger's vector).
The dislocation thus relieves the strain in the channel region, thereby lowering the strain effect in the channel region for carrier mobility enhancement. This results in degradation of the performance of semiconductor devices, and increased fluctuation and variation in device characteristics.